The present invention concerns distributed time-multiplexed bus architecture and emulation apparatus, and more particularly to a time-multiplexed bus circuit and system that greatly reduces propagation delay in emulation or prototyping systems.
Electronics systems generally involve the connection of two or more system components together via a high speed data channel. In order to save on system costs the number of data channels or data buses is usually kept to a minimum. The same data channel is often used to transfer data between multiple system components in either direction and may also be used to transfer data from one component to several other components in a broadcast mode. In order to optimize the overall system performance it is necessary to minimize the amount of time that the data channel is idle between data transfers and to maximize the rate at which data can be transferred.
In a typical system, there is an arbitration logic block that determines which system block is allowed to initiate a data transfer at any given time. This prevents two different system components from transferring data at the same time on the same data channel and thus corrupting each other's data. Typically a system component will request the use of the data channel from the arbitration unit and when the data channel is free that component will be granted the use of the data channel. The system component can then start transferring data on the data channel. There is generally a delay between when the system component is granted the use of the data channel and when it is capable of starting an actual data transfer because the system component must recognized the grant signal and then enable its data buffers to the data bus. In a synchronous system, this delay is at a minimum one clock period but can be longer. This leaves the data channel unused for some period of time and consequently degrades the overall system performance.
IBM in its distributed multiplexer (see patent cited below) breaks the data channel interface into two pieces. One piece is a data node local to each system component that is used to set up the data that is to be transferred on the data channel the clock period prior to data actual being driven on the data channel. The other piece is a multiplexer component that connects to the data channel. This is done to minimize the time delay to actually make the transfer, since only the time delay of the multiplexer component is involved (not the setup and delay of the local data node portion of the circuitry). In this scheme, each system component multiplexer has a data input bus and a data output bus. The data output bus is a logic OR of the component's internal data from the local data node piece and the input data bus of the multiplexer portion of the circuitry. There is then a system level bus grant signal that comes from the arbitration logic that is used to enable the internal data into the logic OR. Throughout the system the output data bus of one component is connected to the input bus of the next component in a daisy-chain fashion. The arbitration logic is responsible for enabling only one system component at a time. The result is that the data bus always contains the data driven from the enabled component without any clock delays needed for a system component to decode a grant signal and then sequentially enable data bus buffers.
Such a distributed multiplexing scheme is slow when used in a system where the data bus is a time-multiplexed bus. This is true because in a time-multiplexed system it takes one timeslot or clock cycle to transfer data through each system component's logic OR. Thus for a system with five components in the bus chain, it would take five timeslots to transfer the correct data throughout the data channel. The current invention reduces the number of timeslots necessary to get the correct data on the data bus to one.
Wired-OR buses are commonly used in computer systems today, as are distributed multiplexers, and both have been used in emulation systems. See, for example, U.S. Pat. No. 5,425,022 assigned to British Telecom entitled DATA SWITCHING NODES; U.S. Pat. No. 5,789,966 assigned to IBM entitled DISTRIBUTED MULTIPLEXER; and U.S. Pat. No. 5,596,742 assigned to MIT entitled VIRTUAL INTERCONNECTIONS FOR RECONFIGURABLE LOGIC SYSTEMS.